1. Field of the Invention
The present invention relates to a semiconductor device, for example, a semiconductor integrated circuit including highly-dense interconnection patterns, such as DRAM (Dynamic Random Access Memory), SRAM (Static Random Access Memory), ROM (Read Only Memory), flash memory and SoC (System-on-Chip).
2. Description of the Related Art
Prior art (JP-11-307531A (1999)) refers to voids generated in interlayer insulation films as interconnections is further minimized. More specifically, narrower interconnections other than those of via contact sections are formed so as to suppress generation of voids, and also the volume of the voids in an entire IC is reduced so as to prevent burst failure of IC which may be caused by void swelling during heat treatment in manufacturing IC.
However, in the prior art, a void exists on the lateral side of the via contact section, and therefore when a via hole is displaced, it may easily come into contact with the void. This inevitably causes such problems as invasion of metal materials and intrusion of polymer cleaning liquid into the aforementioned void.
In recent years, highly-dense interconnections are being developed in such fields as semiconductor memories, and the mass production of flash memories with an interconnection pitch of 70 nm has just started in 2007. In the future, highly-dense interconnections with a pitch narrower than 70 nm will be demanded.
FIG. 7A is a plan view showing an example of layout of an interconnection pattern in a flash memory, which was previously studied by the present inventor, and FIG. 7B is a central cross sectional view of FIG. 7A. Generally, flash memories have a plurality of interconnection layers, with the interconnection layer nearest to a semiconductor substrate having the highest interconnection density.
FIG. 7A illustrates a part of an interconnection pattern of the lowermost layer, in which the interconnection pattern is designed with a pitch of 140 nm including interconnections W with a width of 70 nm and inter-interconnection spaces with a width of 70 nm (i.e., L(line)/S(Space)=70/70 nm).
As shown in FIG. 7B, an interlayer insulation film IL is embedded in between interconnection layers, and a via hole H is formed to establish vertical electric connection between the interconnection layers. The via hole H generally has a tapered shape with an upper diameter larger than a lower (substrate-side) diameter, which is attributed to manufacturing process. In the case of designing the interconnections with a pitch of 140 nm, the smallest via hole H is so formed that a lower diameter has a standard value of, for example, 130 nm (minimum value of 110 nm and maximum value of 150 nm) and an upper diameter has a standard value of 180 nm.
Therefore, as shown in FIG. 7A, two adjacent interconnection lines are partially joined to obtain a contact region in a generally square shape of 210 nm in width×210 nm in length, and the via holes H as described above is placed so as to be aligned with the center of the contact region.
When interconnections of a narrow pitch (e.g., inter-interconnection space is 80 nm or less) are embedded in the insulation film layer, a minute void (cavity) V may be generated between interconnection lines as shown in FIG. 7B. Such voids appear in various places of the narrow pitch space between interconnection lines as shown in FIG. 7A.
Meanwhile, the via hole H is sometimes displaced from the center of the contact region due to, e.g., mask alignment error during lithography process. Assuming that the displacement of the via hole H is isotropic with respect to the center of the contact region, a maximum shift range RA of the via hole H can be expressed as a circumscribed circle of the displaced via holes H as shown in FIG. 7A.
If the via hole H is greatly displaced to come into contact with the void V in between interconnection lines as shown in FIG. 7B, metal materials of the via hole (such as Ti, TiN, W, etc. in case of W (tungsten) plug) may invade into the void V, which may lead to deterioration of reliability, such as interline TDDB (Time Dependence on Dielectric Breakdown).
Moreover, during polymer washing process after etching of the hole, chemical may enter into the void, and as a consequence, when a metal material is deposited on the inner surface of the hole to create the via hole H, deposition of the metal material may be failed due to generation of gas (degas) from the chemical.
In order to control voids causing such failure, it is generally necessary to either increase the interconnection pitch so as to expand the space width between interconnections or decrease the thickness of the metal layer so as to reduce the interconnection height. However, the former solution leads to expansion of a chip area and decrease in interconnection density, whereas the latter solution causes increase in interconnection resistance.